1. Field of the Invention
This invention relates to semiconductor devices and more particularly to a method of manufacturing semiconductor packaging.
2. Description of Related Art
U.S. Pat. No. 5,497,545 of Watanabe et al. for “Method of Making Electrical Connections in the Manufacture of Wiring Sheet Assemblies” describes a multilayer conductor stack formed on a polyimide or ceramic carrier having first and second conductor separated by an insulator sheet are electrically interconnected by a stud inserted through a hole formed in the second conductor and the insulator sheet. Wire bonding and stamping secure the stud to the conductors, thereby forming an electrical connection.
U.S. Pat. No. 5,654,590 of Kuramochi for “Multichip-Module Having an HDI and a Temporary Supporting Substrate” starts with a bonding layer composed of a material such as silicon, aluminum or epoxy resin formed over a temporary supporting base with a temporary supporting layer composed of a material such as SiO2 or various glasses. Then an insulating layer is formed over the bonding layer with throughholes. Next a copper interconnection layer is formed and patterned lithographically. Several alternate insulating layers and interconnection layers with coaxial throughholes are formed. The interconnection layers are also connected by vias. The resulting chip supporting substrate is then separated from the temporary supporting base by etching away the temporary supporting layer of SiO2 or glass with an etchant such as HF, NH4F or a mixture of NH4F and H3PO4. Butyl acetate and acetone are suggested to etch away the epoxy resin.
U.S. Pat. No. 5,965,933 of Young et al. for “Semiconductor Packaging Apparatus” starts the process of manufacture with a thick silicon wafer in which microelectronic devices are to be formed in a device area. Contact cavities have been etched in the top surface of the thick wafer in a pattern surrounding the device area. The contact cavities are filled with via pads composed of refractory metal such as titanium, titanium tungsten or a silicide. Then a semiconductor device is formed in the device area and interconnnects are formed along with an intermediate dielectric layer which is formed above the entire thick silicon wafer including the device, the interconnects and the vias. A cover wafer formed of a semiconductor such as silicon is formed over the intermediate dielectric layer and bonded to the thick silicon wafer. Then the thick silicon wafer is thinned by removing material from the bottom surface thereof until the bottom surfaces of the vias are exposed. Conventional bump contacts are formed on the bottom surfaces of the vias. Alternatively, there is the possibility of forming the vias in the cover wafer instead of the thick silicon wafer by preforming vias in holes in the cover wafer, followed by bonding the cover wafer over the intermediate dielectric layer, the interconnect and the thick silicon wafer. Then the cover wafer is thinned to open the via holes, etc. Next the via holes are filled with metal and bump contacts are formed over the metal vias.
U.S. Pat. No. 6,184,060 of Siniaguine for “Integrated Circuits and Methods for Their Fabrication” describes formation of vias and contact pads on the back side of a silicon semiconductor chip. The vias and contact pads are formed by the process starting with forming tapered vias (openings) in the back of a workpiece comprising a silicon wafer by with an isotropic plasma etch of the via opening down into the silicon wafer through an aluminum or photoresist mask formed over the silicon. The via openings have a depth at least as large as the final thickness of the wafer after the manufacturing process is completed. After the mask is removed, a thin conformal, glass or BPSG dielectric layer (1-2 μm thick) is formed over the substrate including the vias. Then a thin conformal blanket conductive layer (e.g. 0.8-1.2 μm thick) is formed over the dielectric layer of aluminum, gold or nickel. A planar glass layer is spun onto the surface of the conductive layer to fill the vias to provide a planar top surface of the wafer. The conductive layer may or may not have been patterned before the last step of filling the vias with the planar glass layer. Other layers to be a part of the device structure are then formed on top of the planarized surface of the workpiece including a dielectric layer and contact pads. Then the back side of the silicon wafer is etched by an atmospheric plasma etch with argon and carbon tetrafluoride in air. When the glass or BPSG dielectric layer becomes exposed, the silicon substrate is preferentially etched relative to the silicon dioxide dielectric layer by almost an order of magnitude difference with the silicon etching far more quickly. Thus, the portions of the lower surface (back side) of the conductive layer formed in the via openings comprise contact pads for the back side of the chip which are exposed by the preferential etching away of the silicon.
U.S. Pat. No. 5,258,235 of Arjavalingam et al. for “Multilayer Thin Film Structure and Parallel Process in Method for Fabricating Same” describes releasing a structure from a substrate by a laser ablation shining a laser beam through the substrate to ablate the polyimide film. The result is that the polyimide film releases the structure.
Matsuo et al. “Silicon Interposer Technology for High-density Package” Electronic Components and Technology Conference, IEEE, 4 pages (2000) describes a fabrication process in which through hole 30 μm in diameter and 60 μm deep was etched anisotropically by a “high-speed RIE process” resulting in a hole with nearly vertical sidewalls. After coating the wafer with silicon dioxide, the through hole was filled with Cu by electroplating onto a Cu/TaN seed layer. After many intervening steps, the wafer was thinned until exposing the through plug by BSG. The vertical sidewalls of the through hole may present a problem with regard to the mechanical integrity of the ultimate thin wafer because of stresses generated by the mismatch of the characteristics of the silicon and the copper. Such thin wafers with inherent stresses may be difficult to handle through normal handling during the fabrication of multilevel wiring processes.
One of the problems with using silicon based structures for electronic packaging applications is to be able to provide a highly reliable product by employing an efficient method of forming vias through a membrane thin silicon substrate, i.e. from the bottom surface through the silicon to the top of the silicon where the wiring structure is fabricated. That requires forming the vias without breaking the fragile membrane thin wafer and yet performing the task with a highly competitive manufacturing cost.
See U.S. Pat. No. 6,036,809 of Kelly et al. and U.S. Pat. No. 6,066,562 of Ohshima et al.